As the use of electronic devices, such as personal computers, continue to increase, it is becoming ever more important to make such devices portable. The usefulness of portable electronic devices, such as notebook computers, is limited by the limited length of time batteries are capable of powering the device before needing to be recharged. This problem has been addressed by attempts to increase battery life and attempts to reduce the rate at which such electronic devices consume power.
Various techniques have been used to reduce power consumption in electronic devices, the nature of which often depends upon the type of power consuming electronic circuits that are in the device. For example, electronic devices such a notebook computers, typically include dynamic random access memory (“DRAM”) devices that consume a substantial amount of power. As the data storage capacity and operating speeds of DRAM devices continues to increase, the power consumed by such devices has continued to increase in a corresponding manner.
In general, the power consumed by a DRAM device increases with both the capacity and the operating speed of the DRAM devices. The power consumed by DRAM devices is also affected by their operating mode. A DRAM device for example, will generally consume a relatively large amount of power when the memory cells of the DRAM device are being refreshed. As is well-known in the art, DRAM memory cells, each of which essentially consists of a capacitor, must be periodically refreshed to retain data stored in the DRAM device. Refresh is typically performed by essentially reading data bits from the memory cells in each row of a memory cell array and then writing those same data bits back to the same cells in the row. A relatively large amount of power is consumed when refreshing a DRAM because rows of memory cells in a memory cell array are being actuated in the rapid sequence. Each time a row of memory cells is actuated, a pair of digit lines for each memory cell are switched to complementary voltages and then equilibrated. As a result, DRAM refreshes tends to be particularly power-hungry operations. Further, since refreshing memory cells must be accomplished even when the DRAM is not being used and is thus inactive, the amount of power consumed by refresh is a critical determinant of the amount of power consumed by the DRAM over an extended period. Thus many attempts to reduce power consumption in DRAM devices have focused on reducing the rate at which power is consumed during refresh.
Refresh power can, of course, be reduced by reducing the rate at which the memory cells in a DRAM are being refreshed. However, reducing the refresh rate increases the risk that data stored in the DRAM memory cells will be lost. More specifically, since, as mentioned above, DRAM memory cells are essentially capacitors, charge inherently leaks from the memory cell capacitors, which can change the value of a data bit stored in the memory cell over time. However, current leaks from capacitors at varying rates. Some capacitors are essentially short-circuited and are thus incapable of storing charge indicative of a data bit. These defective memory cells can be detected during production testing, and can then be repaired by substituting non-defective memory cells using conventional redundancy circuitry. On the other hand, current leaks from most DRAM memory cells at much slower rates that span a wide range. A DRAM refresh rate is chosen to ensure that all but a few memory cells can store data bits without data loss. This refresh rate is typically once every 64 ms. The memory cells that cannot reliably retain data bits at this refresh rate are detected during production testing and replaced by redundant memory cells.
One technique that has been used to prevent data errors is to generate an error correcting code “ECC,” which is known as a “syndrome,” from each item of stored data, and then store the syndrome along with the data. When the data are read from the memory device, the syndrome is also read, and it is then used to determine if any bits of the data are in error. As long as not too many data bits are in error, the syndrome may also be used to correct the read data.
A conventional computer system 10 employing ECC techniques is shown in FIG. 1. The computer system 10 includes a central processor unit (“CPU”) 14 coupled to a system controller 16 through a processor bus 18. The system controller 16 is coupled to input/output (“I/O”) devices (not shown) through a peripheral bus 20 and to an I/O controller 24 through an expansion bus 26. The I/O controller 24 is also connected to various peripheral devices (not shown) through an I/O bus 28.
The system controller 16 includes a memory controller 30 that is coupled to a dynamic random access memory (“DRAM”) 32 through an address bus 36, a control bus 38, a syndrome bus 40, and a data bus 42. The DRAM 32 includes an array 34 of memory cells that stores data and a syndrome coupled through the data bus 42 and the syndrome bus 40, respectively. The locations in the DRAM 32 to which data are written and data are read are designated by addresses coupled to the DRAM 32 on the address bus 36. The operation of the DRAM is controlled by control signals coupled to the DRAM 32 on the control bus 38. These control signals can cause the DRAM 32 to operate in various refresh modes, such as a “self-refresh” mode in periodic refresh cycles are periodically initiated without the need to apply control signals to the DRAM 32. The DRAM 32 also includes a mode register 44 that stores several bits that can be set or reset to control the operating mode of the DRAM 32.
When data are to be written to the DRAM 32, the memory controller 30 generates a syndrome and then couples the syndrome and the write data to the DRAM 32 through the syndrome bus 40 and the data bus 42, respectively. The memory controller 30 also couples control signals to the DRAM 32 through the control bus 38 and a memory address through the address bus 36. The data are then stored in an array 34 of DRAM memory cells. When the stored data are to be read from the DRAM 32, the memory controller 30 applies control signals to the DRAM 32 through the control bus 38 and a memory address to the DRAM 32 through the address bus 36. Read data and the corresponding syndrome are then coupled from the DRAM 32 to the memory controller 30 through the data bus 42 and syndrome bus 40, respectively. The memory controller 30 then uses the syndrome to determine if any bits of the read data are in error, and, if not too many bits are in error, to correct the read data.
The use of ECC techniques can significantly improve the reliability of data stored in the DRAM 32. Furthermore, the use of ECC techniques could allow the DRAM 32 to be refreshed at a slower refresh rate since resulting data bit errors could be corrected. The use of a slower refresh rate could provide the significant advantage of reducing the power consumed by the DRAM 32. However, if the memory controller 30 was not operating in an ECC mode when the DRAM 32 entered a refresh cycle, it would be necessary to perform the refresh at the normal, relatively high rate. Using ECC techniques as the DRAM 32 enters refresh will not suffice to allow refresh to occur at a reduced rate because no ECC syndromes will have been stored in the DRAM 32 at that time. Further, if the memory controller 30 is performing an ECC function, the reduced power advantages made possible by using ECC techniques would not be obtained unless the operation of the DRAM 32 was altered to take advantage of the ECC capability by reducing the refresh rate.
There is therefore a need for a memory system and method that is effective in allowing a DRAM to operate in a reduced power refresh mode by using ECC techniques to correct errors that might develop during the reduced power refresh.